By Bruce Wile
One of many greatest demanding situations in chip and process layout is figuring out no matter if the works safely. that's the activity of useful verification engineers and they're the viewers for this complete textual content from 3 most sensible professionals.
As designs raise in complexity, so has the price of verification engineers in the layout group. in truth, the necessity for experienced verification engineers has grown dramatically--functional verification now consumes among forty and 70% of a project's hard work, and approximately part its price. presently there are only a few books on verification for engineers, and none that hide the topic as comprehensively as this article.
A key energy of this publication is that it describes the total verification cycle and information each one degree. The association of the booklet follows the cycle, demonstrating how useful verification engages all facets of the general layout attempt and the way person cycle phases relate to the bigger layout procedure. in the course of the textual content, the authors leverage their 35 plus years event in practical verification, offering examples and case reports, and concentrating on the talents, equipment, and instruments had to whole each one verification activity. also, the key proprietors (Mentor images, Cadence layout platforms, Verisity, and Synopsys) have carried out key examples from the textual content and made those to be had online, in order that the reader can try out the equipment defined within the textual content.
* finished evaluation of the full verification cycle
* Combines adventure with a powerful emphasis on sensible verification fundamentals
* contains real-world case stories and downloadable software program implementations of key examples from the main proprietors (Mentor photos, Cadence layout structures, Verisity, and Synopsys)
Read or Download Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon) PDF
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