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Semiconductors

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By Steven H. Voldman

Curiosity in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) expertise, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration.

Clear methodologies that furnish security from latchup, with perception into the physics, know-how and circuit matters concerned, are in expanding demand.

This booklet describes CMOS and BiCMOS semiconductor expertise and their sensitivity to offer day latchup phenomena, from simple over-voltage and over-current stipulations, unmarried occasion latchup (SEL) and cable discharge occasions (CDE), to latchup domino phenomena. It comprises chapters targeting bipolar physics, latchup concept, latchup and safeguard ring characterization buildings, characterization checking out, product point attempt structures, product point trying out and experimental effects. Discussions on state of the art semiconductor procedures, layout structure, and circuit point and process point latchup options also are integrated, to boot as:

  • latchup semiconductor technique suggestions for either CMOS to BiCMOS, reminiscent of shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers,  and buried grids – from unmarried- to triple-well CMOS; 
  • practical latchup layout tools, computerized and bench-level latchup checking out equipment and methods, latchup conception of logarithm resistance area, generalized alpha  (a) house, beta (b) area, new latchup layout tools– connecting the theoretical to the sensible research, and;
  • examples of  latchup desktop aided layout (CAD) methodologies, from layout rule checking (DRC) and logical-to-physical design,  to new latchup CAD methodologies that deal with latchup for inner and exterior latchup on a neighborhood in addition to worldwide layout level.

Latchup acts as a spouse textual content to the author’s sequence of books on ESD (electrostatic discharge) security, serving as a useful reference for the pro semiconductor chip and system-level ESD engineer. Semiconductor machine, method and circuit designers, and caliber, reliability and failure research engineers will locate it informative at the concerns that confront glossy CMOS technology.  Practitioners within the car and aerospace industries also will locate it priceless. moreover, its educational therapy will entice either senior and graduate scholars with pursuits in semiconductor approach, equipment physics, computing device aided layout and layout integration.

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